Binding Options

-binding

Use this option to pin or bind MPI processes to a particular processor and avoid undesired process migration. In the following syntax, the quotes may be omitted for a one-member list. Each parameter corresponds to a single pinning property.

This option is supported on both IntelĀ® and non-Intel microprocessors, but it may perform additional optimizations for Intel microprocessors than it performs for non-Intel microprocessors.

Syntax

-binding "<parameter>=<value>[;<parameter>=<value> ...]"

Parameters

pin

Pinning switch

enable | yes | on | 1

Turn on the pinning property. This is the default value

disable | no | off | 0

Turn off the pinning property

 

cell

Pinning resolution

unit

Basic processor unit (logical CPU)

core

Processor core in multi-core system

 

map

Process mapping

spread

The processes are mapped consecutively to separate processor cells. Thus, the processes do not share the common resources of the adjacent cells.

scatter

The processes are mapped to separate processor cells. Adjacent processes are mapped upon the cells that are the most remote in the multi-core topology.

bunch

The processes are mapped to separate processor cells by #processes/#sockets processes per socket. Each socket processor portion is a set of the cells that are the closest in the multi-core topology.

p0,p1,...,pn

The processes are mapped upon the separate processors according to the processor specification on the p0,p1,...,pn list: theith process is mapped upon the processor pi, where

pi takes one of the following values:

  • processor number like n

  • range of processor numbers like n-m

  • -1 for no pinning of the corresponding process

[m0,m1,...,mn]

The ith process is mapped upon the processor subset defined by mi hexadecimal mask using the following rule:

The jth processor is included into the subset mi if the jth bit of mi equals 1.

 

domain

Processor domain set on a node

cell

Each domain of the set is a single processor cell (unit or core).

core

Each domain of the set consists of the processor cells that share a particular core.

cache1

Each domain of the set consists of the processor cells that share a particular level 1 cache.

cache2

Each domain of the set consists of the processor cells that share a particular level 2 cache.

cache3

Each domain of the set consists of the processor cells that share a particular level 3 cache.

cache

The set elements of which are the largest domains among cache1, cache2, and cache3

socket

Each domain of the set consists of the processor cells that are located on a particular socket.

node

All processor cells on a node are arranged into a single domain.

<size>[:<layout>]

Each domain of the set consists of <size> processor cells. <size> may have the following values:

  • auto - domain size = #cells/#processes

  • omp - domain size = OMP_NUM_THREADS environment variable value

  • positive integer - exact value of the domain size

Note

Domain size is limited by the number of processor cores on the node.

Each member location inside the domain is defined by the optional <layout> parameter value:

  • compact - as close with others as possible in the multi-core topology

  • scatter - as far away from others as possible in the multi-core topology

  • range - by BIOS numbering of the processors

If <layout> parameter is omitted, compact is assumed as the value of <layout>

 

order

Linear ordering of the domains

compact

Order the domain set so that adjacent domains are the closest in the multi-core topology

scatter

Order the domain set so that adjacent domains are the most remote in the multi-core topology

range

Order the domain set according to the BIOS processor numbering

 

offset

Domain list offset

<n>

Integer number of the starting domain among the linear ordered domains. This domain gets number zero. The numbers of other domains will be cyclically shifted.